Ball lens embedded through-package via to enable backside coupling between silicon photonics interposer and board-level interconnects

Development of an efficient and densely integrated optical coupling interface for silicon photonics based board-level optical interconnects is one of the key challenges in the domain of 2.5D/3D electro-optic integration. Enabling high-speed on-chip electro-optic conversion and efficient optical transmission across package/board-level short-reach interconnections can help overcome the limitations of a conventional electrical I/O in terms of bandwidth density and power consumption in a high-performance computing environment. In this context, we have demonstrated a novel optical coupling interface to integrate silicon photonics with board-level optical interconnects. We show that by integrating a ball lens in a via drilled in an organic package substrate, the optical beam diffracted from a downward directionality grating on a photonics chip can be coupled to a board-level polymer multimode waveguide with a good alignment tolerance. A key result from the experiment was a 14 chip-to-package 1-dB lateral alignment tolerance for coupling into a polymer waveguide with a cross-section of 20 x 25. An in-depth analysis of loss distribution across several interfaces was done and a -3.4 dB coupling efficiency was measured between the optical interface comprising of output grating, ball lens and polymer waveguide. Furthermore, it is shown that an efficiency better than -2 dB can be achieved by tweaking few parameters in the coupling interface. The fabrication of the optical interfaces and related measurements are reported and verified with simulation results

Expanded-beam backside coupling interface for alignment-tolerant packaging of silicon photonics

We demonstrate an alignment-tolerant backside coupling interface in the O-band for silicon photonics by generating an optimized through-substrate (downward) directionality beam from a TE-mode grating coupler and hybrid integrating the chip with backside silicon microlenses to achieve expanded beam collimation. The key advantage of using such an expanded beam interface is an increased coupling tolerance to lateral and longitudinal misalignment. A 34 mu m beam diameter was achieved over a combined substrate thickness of 630 mu m which was then coupled to a thermally expanded core single-mode fiber to investigate the tolerances. A 1-dB fiber-to-microlens lateral alignment tolerance of 14 mu m and an angular alignment tolerance of 1 degrees was measured at a wavelength of 1310 nm. In addition, a large +/- 2.5 mu m 1-dB backside alignment accuracy was measured for the placement of microlens with respect to the grating. The radius of curvature of Si microlens to achieve a collimated beam was 480 mu m, and a 1-dB longitudinal alignment tolerance of 700 mu m was measured for coupling to a single-mode expanded core fiber. The relaxation in alignment tolerances make the demonstrated coupling interface suitable for chip-to-package or chip-to-board couplin

Design optimization for energy-efficient pulse-switching networks in carrier-injection based Si-photonics

We compare pulse-switching operations in MZI- and ring-switches both experimentally and based on large-signal circuit simulations. With a modification in switch design and with optimization of phase modulator lengths, we show high-speed switches with potential for an over 3 dB improvement in energy consumption

Impact of optical free-carrier generation on the performance of SOI phase shifters

We provide measurement and simulation data of optical free-carrier generation in SOI phase shifters. We conclude that phase impairments caused by unwanted free-carriers can be equalized with an similar to 50% increase in phase shifter diode current. (c) 2020 The Author(s

III-V-on-silicon photonic transceivers

In this paper we give an overview on our work on silicon photonic high-speed transceivers and the co-integration of III-V opto-electronic components on the silicon photonic platform

High-Q photonic crystal nanocavities on 300 mm SOI substrate fabricated with 193 nm immersion lithography

On-chip 1-D photonic crystal nanocavities were designed and fabricated in a 300 mm silicon-on-insulator wafer using a CMOS-compatible process with 193 nm immersion lithography and silicon oxide planarization. High quality factors up to 10(5) were achieved. By changing geometrical parameters of the cavities, we also demonstrated a wide range of wavelength tunability for the cavity mode, a low insertion loss and excellent agreement with simulation results. These on-chip nanocavities with high quality factors and low modal volume, fabricated through a high-resolution and high-volume CMOS compatible platform open up new opportunities for the photonic integration community